Website Hire With Jarvis - Rob Lara
Jarvis is working with a leading semiconductor manufacturer looking to bring on a highly skilled and motivated ASIC Post Silicon Validation Engineer to join our team in Montreal. As a Post Silicon Validation Engineer, you will play a crucial role in validating and verifying the functionality and performance of our advanced ASIC designs.
- Develop and execute post silicon validation plans: Design comprehensive validation plans, test cases, and strategies to validate ASIC designs on silicon, including functional validation, performance characterization, and compliance testing.
- Debug and resolve issues: Identify and debug design and validation issues using industry-standard tools and techniques, collaborating closely with cross-functional teams to achieve timely resolutions.
- Design and implement validation environments: Develop and deploy robust and scalable validation environments, including testbenches, simulation models, and scripting infrastructure, to enable efficient and thorough validation.
- Collaborate with design and verification teams: Work closely with design and verification teams to ensure seamless integration of validation methodologies, provide feedback on design improvements, and support overall design verification and release processes.
- ASIC validation experience: Possess a minimum of 5 years of hands-on experience in ASIC validation, with a strong understanding of analog and mixed-signal RF / ASIC design principles and methodologies.
- Proficiency in modeling languages: Strong expertise in modeling languages such as Verilog, along with proficiency in other scripting and programming languages such as MATLAB, Python, and C++.
- Knowledge of simulation and verification tools: Familiarity with industry-standard simulation and verification tools, ensuring efficient and accurate modeling and validation.
- Education: Hold a Master’s or PhD degree in Electrical Engineering or equivalent, with a specialization in ASIC design, modeling, or related field.
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